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? semiconductor components industries, llc, 2013 february, 2013 ? rev. p2 1 publication order number: NCL30082/d NCL30082 product preview dimmable quasi-resonant primary side current-mode controller for led lighting with thermal fold-back the NCL30082 is a pwm current mode controller targeting isolated flyback and non ? isolated constant current topologies. the controller operates in a quasi ? resonant mode to provide high efficiency. thanks to a novel control method, the device is able to precisely regulate a constant led current from the primary side. this removes the need for secondary side feedback circuitry, biasing and an optocoupler. the device is highly integrated with a minimum number of external components. a robust suite of safety protection is built in to simplify the design. this device supports analog/digital dimming as well as thermal current fold ? back. while the NCL30082 has integrated fixed overvoltage protection, the designer has the flexibility to program a lower ovp level. features ? quasi ? resonant peak current ? mode control operation ? primary side sensing (no optocoupler needed) ? wide v cc range ? source 300 ma / sink 500 ma totem pole driver with 12 v gate clamp ? precise led constant current regulation 1% typical ? line feed ? forward for enhanced regulation accuracy ? low led current ripple ? 250 mv 2% guaranteed voltage reference for current regulation ? ~ 0.9 power factor with valley fill input stage ? low start ? up current (13 a typ.) ? analog or digital dimming ? thermal fold ? back ? wide temperature range of ? 40 to +125 c ? pb ? free, halide ? free msl1 product ? robust protection features ? over voltage / led open circuit protection ? over temperature protection ? secondary diode short protection ? output short circuit protection ? shorted current sense pin fault detection ? latched and auto ? recoverable versions ? brown ? out ? v cc under voltage lockout ? thermal shutdown typical applications ? integral led bulbs ? led power driver supplies ? led light engines this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. http://onsemi.com pin connections see detailed ordering and shipping information in the package dimensions section on page 32 of this data sheet. ordering information micro8 dm suffix case 846a marking diagram aax = specific device code x = c or d a = assembly location y = year w = work week = pb ? free package (note: microdot may be in either location) aax ayw 1 8 dim vin vcc drv sd zcd cs gnd (top view) 1
NCL30082 http://onsemi.com 2 1 2 3 45 8 6 7 . . aux . figure 1. typical application schematic for NCL30082 v dim table 1. pin function description pin no pin name function pin description 1 sd thermal fold ? back and shutdown connecting an ntc to this pin allows reducing the output current down to 50% of its fixed value before stopping the controller. a zener diode can also be used to pull ? up the pin and stop the controller for adjustable ovp protection 2 zcd zero crossing detection connected to the auxiliary winding, this pin detects the core reset event. 3 cs current sense this pin monitors the primary peak current 4 gnd ? the controller ground 5 drv driver output the current capability of the totem pole gate drive (+0.3/ ? 0.5 a) makes it suit- able to effectively drive a broad range of power mosfets. 6 vcc supplies the controller this pin is connected to an external auxiliary voltage. 7 vin input voltage sensing brown ? out this pin observes the hv rail and is used in valley selection. this pin also monitors and protects for low mains conditions. 8 dim analog / pwm dimming this pin is used for analog or pwm dimming control. an analog signal than can be varied between v dim(en) and v dim100 can be used to vary the current, or a pwm signal with an amplitude greater than v dim100 .
NCL30082 http://onsemi.com 3 sd zcd zero crossing detection valley selection cs ipkmax wod_scp qdrv vcc management vcc drv internal thermal shutdown management dim dimming type detection enable vin bo_nok cs_reset stop uvlo off latch stop wod_scp ipkmax bo_nok gnd stop qdrv aux. winding aux_scp aux_scp vcc_max offset_ok offset_ok line enable ipkmax enable cs_shorted cs_shorted control constant ? current short circuit prot. clamp circuit winding and output diode short circuit protection max. peak current limit cs short protection leading edge blanking feedforward over voltage protection over temperature protection thermal foldback fault protection vcc over voltage brown ? out s r q figure 2. internal circuit architecture v tf v vin v dima v ref v tf v vly v vin v vin v ref v vin v dima v cc v ref v dd
NCL30082 http://onsemi.com 4 table 2. maximum ratings table symbol rating value unit v cc(max) i cc(max) maximum power supply voltage, vcc pin, continuous voltage maximum current for vcc pin ? 0.3, +35 internally limited v ma v drv(max) i drv(max) maximum driver pin voltage, drv pin, continuous voltage maximum current for drv pin ? 0.3, v drv (note 1) ? 500, +800 v ma v max i max maximum voltage on low power pins (except pins zcd, dim, drv and vcc) current range for low power pins (except pins zcd, drv and vcc) ? 0.3, +5.5 ? 2, +5 v ma v zcd(max) i zcd(max) maximum voltage for zcd pin maximum current for zcd pin ? 0.3, +10 ? 2, +5 v ma v dim(max) maximum voltage for dim pin ? 0.3, +10 v r j ? a thermal resistance, junction ? to ? air 289 c/w t j(max) maximum junction temperature 150 c operating temperature range ? 40 to +125 c storage temperature range ? 60 to +150 c esd capability, hbm model (note 2) 4 kv esd capability, mm model (note 2) 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. v drv is the drv clamp voltage v drv(high) when v cc is higher than v drv(high) . v drv is v cc unless otherwise noted. 2. this device series contains esd protection and exceeds the following tests: human body model 4000 v per mil ? std ? 883, method 3015. 3. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78 except for vin pin which passes 60 ma.
NCL30082 http://onsemi.com 5 table 3. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v; for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v) description test condition symbol min typ max unit startup and supply circuits supply voltage startup threshold minimum operating voltage hysteresis v cc(on) ? v cc(off) internal logic reset v cc increasing v cc decreasing v cc decreasing v cc(on) v cc(off) v cc(hys) v cc(reset) 16 8.2 8 3.5 18 8.8 ? 4.5 20 9.4 ? 5.5 v over voltage protection vcc ovp threshold v cc(ovp) 26 28 30 v v cc(off) noise filter v cc(reset) noise filter ? t vcc(off) t vcc(reset) ? ? 5 20 ? ? s startup current i cc(start) ? 13 30 a startup current in fault mode i cc(sfault) ? 46 60 a supply current device disabled/fault device enabled/no output load on pin 5 device switching (f sw = 65 khz) v cc > v cc(off) f sw = 65 khz c drv = 470 pf, f sw = 65 khz i cc1 i cc2 i cc3 0.8 ? ? 1.2 2.3 2.7 1.4 4.0 5.0 ma current sense maximum internal current limit v ilim 0.95 1 1.05 v leading edge blanking duration for v ilim (t j = ? 25 c to 125 c) t leb 250 300 350 ns leading edge blanking duration for v ilim (t j = ? 40 c to 125 c) t leb 240 300 350 ns input bias current drv high i bias ? 0.02 ? a propagation delay from current detection to gate off ? state t ilim ? 50 150 ns threshold for immediate fault protection activation v cs(stop) 1.35 1.5 1.65 v leading edge blanking duration for v cs(stop) t bcs ? 120 ? ns blanking time for cs to gnd short detection v pinvin = 1 v t cs(blank1) 6 ? 12 s blanking time for cs to gnd short detection v pinvin = 3.3 v t cs(blank2) 2 ? 4 s gate drive drive resistance drv sink drv source r snk r src ? ? 13 30 ? ? drive current capability drv sink (note 4) drv source (note 4) i snk i src ? ? 500 300 ? ? ma rise time (10% to 90%) c drv = 470 pf t r ? 40 ? ns fall time (90% to 10%) c drv = 470 pf t f ? 30 ? ns drv low voltage v cc = v cc(off) +0.2 v c drv = 470 pf, r drv = 33 k v drv(low) 8 ? ? v drv high voltage v cc = 30 v c drv = 470 pf, r drv = 33 k v drv(high) 10 12 14 v 4. guaranteed by design 5. otp triggers when r ntc = 4.7 k
NCL30082 http://onsemi.com 6 table 3. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v; for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v) description unit max typ min symbol test condition zero voltage detection circuit zcd threshold voltage v zcd increasing v zcd(thi) 25 45 65 mv zcd threshold voltage (note 4) v zcd decreasing v zcd(thd) 5 25 45 mv zcd hysteresis (note 4) v zcd increasing v zcd(hys) 10 ? ? mv threshold voltage for output short circuit or aux. winding short circuit detection v zcd(short) 0.8 1 1.2 v short circuit detection timer v zcd < v zcd(short) t ovld 70 90 110 ms auto ? recovery timer duration t recovery 3 4 5 s input clamp voltage high state low state i pin1 = 3.0 ma i pin1 = ? 2.0 ma v ch v cl ? ? 0.9 9.5 ? 0.6 ? ? 0.3 v propagation delay from valley detection to drv high v zcd decreasing t dem ? ? 150 ns equivalent time constant for zcd input (note 4) t par ? 20 ? ns blanking delay after on ? time t blank 2.25 3 3.75 s timeout after last demag transition t timo 5 6.5 8 s constant current control reference voltage at t j = 25 c v ref 245 250 255 mv reference voltage t j = ? 40 c to 125 c v ref 242.5 250 257.5 mv 50% reference voltage (for thermal foldback) v ref50 ? 125 ? mv current sense lower threshold for detection of the leakage inductance reset time v cs(low) 30 55 80 mv line feed ? forward v vin to i cs(offset) conversion ratio k lff 15 17 19 a/v offset current maximum value v pinvin = 4.5 v i offset(max) 67.5 76.5 85.5 a v ref value below which the offset current source is turned off v ref decreases v ref(off) ? 37.5 ? mv v ref value above which the offset current source is turned on v ref increases v ref(on) ? 50 ? mv valley selection threshold for line range detection v in increasing (1 st to 2 nd valley transition for v ref > 0.75 v) v vin increases v hl 2.28 2.4 2.52 v threshold for line range detection v in decreasing (2 nd to 1 st valley transition for v ref > 0.75 v) v vin decreases v ll 2.18 2.3 2.42 v blanking time for line range detection t hl(blank) 15 25 35 ms valley thresholds 1 st to 2 nd valley transition at ll and 2 nd to 3 rd valley hl 2 nd to 1 st valley transition at ll and 3 rd to 2 nd valley hl 2 nd to 4 th valley transition at ll and 3 rd to 5 th valley hl 4 th to 2 nd valley transition at ll and 5 th to 3 rd valley hl 4 th to 7 th valley transition at ll and 5 th to 8 th valley hl 7 th to 4 th valley transition at ll and 8 th to 5 th valley hl 7 th to 11 th valley transition at ll and 8 th to 12 th valley hl 11 th to 7 th valley transition at ll and 12 th to 8 th valley hl 11 th to 13 th valley transition at ll and 12 th to 15 th valley hl 13 th to 11 th valley transition at ll and 15 th to 12 th valley hl v ref decreases v ref increases v ref decreases v ref increases v ref decreases v ref increases v ref decreases v ref increases v ref decreases v ref increases v vly1 ? 2/2 ? 3 v vly2 ? 1/3 ? 2 v vly2 ? 4/3 ? 5 v vly4 ? 2/5 ? 3 v vly4 ? 7/5 ? 8 v vly7 ? 4/8 ? 5 v vly7 ? 11/8 ? 12 v vly11 ? 7/12 ? 8 v vly11 ? 13/12 ? 15 v vly13 ? 11/15 ? 12 177.5 185.0 117.5 125.0 ? ? ? ? ? ? 187.5 195.0 125.0 132.5 75.0 82.5 37.5 50.0 15.0 20.0 197.5 205.0 132.5 140.0 ? ? ? ? ? ? mv 4. guaranteed by design 5. otp triggers when r ntc = 4.7 k
NCL30082 http://onsemi.com 7 table 3. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v; for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v) description unit max typ min symbol test condition dimming section dim pin voltage for zero output current (off voltage) v dim(en) 0.66 0.7 0.74 v dim pin voltage for maximum output current v dim100 2.25 2.45 2.65 v dimming range v dim(range) ? 1.75 ? v clamping voltage for dim pin v dim(clp) ? 7.8 ? v dimming pin pull ? up current source i dim(pullup) ? 280 ? na thermal fold ? back and ovp sd pin voltage at which thermal fold ? back starts v tf(start) 0.9 1 1.2 v sd pin voltage at which thermal fold ? back stops (i out = 50% i out(nom) ) v tf(stop) 0.64 0.68 0.72 v reference current for direct connection of an ntc (note 5) i otp(ref) 80 85 90 a fault detection level for otp (note 5) v sd decreasing v otp(off) 0.47 0.5 0.53 v sd pin level at which controller re ? start switching after otp detection v sd increasing v otp(on) 0.64 0.68 0.72 v timer duration after which the controller is allowed to start pulsing (note 5) t otp(start) 180 ? 300 s clamped voltage (sd pin left open) sd pin open v sd(clamp) 1.13 1.35 1.57 v clamp series resistor r sd(clamp) ? 1.6 ? k sd pin detection level for ovp v sd increasing v ovp 2.35 2.5 2.65 v delay before ovp or otp confirmation (ovp and otp) t sd(delay) 15 30 45 s thermal shutdown thermal shutdown (note 4) device switching (f sw around 65 khz) t shdn 130 150 170 c thermal shutdown hysteresis (note 4) t shdn(hys) ? 50 ? c brown ? out brown ? out on level (ic start pulsing) v sd increasing v bo(on) 0.90 1 1.10 v brown ? out off level (ic shuts down) v sd decreasing v bo(off) 0.85 0.9 0.95 v bo comparators delay t bo(delay) ? 30 ? s brown ? out blanking time t bo(blank) 35 50 65 ms brown ? out pin bias current i bo(bias) ? 250 ? 250 na 4. guaranteed by design 5. otp triggers when r ntc = 4.7 k
NCL30082 http://onsemi.com 8 typical characteristics figure 3. v cc(on) vs. junction temperature figure 4. v cc(off) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 17.90 17.95 18.00 18.05 18.10 18.15 18.20 8.60 8.65 8.70 8.75 8.80 8.85 8.90 figure 5. v cc(ovp) vs. junction temperature figure 6. i cc(start) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 27.50 27.55 27.60 27.65 27.70 27.75 27.80 10 11 12 13 14 16 17 18 figure 7. i cc(sfault) vs. junction temperature figure 8. i cc1 vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 40 42 44 46 48 50 52 1.12 1.14 1.16 1.20 1.22 1.26 1.28 1.30 v cc(on) (v) v cc(off) (v) v cc(ovp) (v) i cc(start) ( a) i cc(sfault) ( a) i cc1 (ma) 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 15 1.18 1.24
NCL30082 http://onsemi.com 9 typical characteristics figure 9. i cc2 vs. junction temperature figure 10. i cc3 vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.70 2.75 2.80 2.85 figure 11. v ilim vs. junction temperature figure 12. v cs(stop) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 0.980 0.985 0.990 0.995 1.000 1.475 1.480 1.485 1.490 1.495 figure 13. t leb vs. junction temperature figure 14. v zcd(short) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 285 287 291 293 295 299 303 305 0.980 0.985 0.990 0.995 1.000 1.005 1.010 i cc2 (ma) i cc3 (ma) v ilim (v) v cs(stop) (v) t leb (ns) v zcd(short) (v) 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 2.65 289 297 301
NCL30082 http://onsemi.com 10 typical characteristics figure 15. t blank vs. junction temperature figure 16. t timo vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 3.00 3.05 3.10 3.15 3.20 6.5 6.6 6.7 6.8 6.9 7.0 7.1 figure 17. v ref vs. junction temperature figure 18. v cs(low) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 249 250 251 252 253 254 255 52.0 52.5 53.0 53.5 54.0 54.5 55.0 figure 19. k lff vs. junction temperature figure 20. v ref(off) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 16.30 16.35 16.40 16.45 16.50 16.55 16.60 37.0 37.1 37.2 37.3 37.4 37.5 37.6 t blank ( s) t timo ( s) v ref (mv) v cs(low) (mv) k lff ( a/v) v ref(off) (mv) 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120
NCL30082 http://onsemi.com 11 typical characteristics figure 21. v ref(on) vs. junction temperature figure 22. v hl vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 44.0 44.5 45.5 46.5 47.0 48.0 49.0 2.370 2.375 2.380 2.385 2.390 2.395 2.400 figure 23. v ll vs. junction temperature figure 24. t hl(blank) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 2.270 2.275 2.280 2.285 2.290 2.295 2.300 26.0 26.5 27.0 27.5 28.0 figure 25. v vly1 ? 2/2 ? 3 vs. junction temperature figure 26. v vly2 ? 1/3 ? 2 vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 184.0 184.5 185.0 185.5 186.0 186.5 187.0 191 192 193 194 195 196 197 198 v ref(on) (mv) v hl (v) v ll (v) t hl(blank) (ms) v vly1 ? 2/2 ? 3 (mv) v vly2 ? 1/3 ? 2 (mv) 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 45.0 46.0 47.5 48.5
NCL30082 http://onsemi.com 12 typical characteristics figure 27. v vly2 ? 4/3 ? 5 vs. junction temperature figure 28. v vly4 ? 2/5 ? 3 vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 122.0 122.5 123.0 123.5 124.0 124.5 125.0 130 131 132 133 134 135 136 figure 29. v vly4 ? 7/5 ? 8 vs. junction temperature figure 30. v vly7 ? 4/8 ? 5 vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 73.0 73.5 74.0 74.5 75.0 75.5 76.0 80 81 82 83 84 85 86 87 figure 31. v vly7 ? 11/8 ? 12 vs. junction temperature figure 32. v vly11 ? 7/12 ? 8 vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 37.0 37.1 37.2 37.3 37.4 37.5 37.6 37.7 43 44 45 46 47 48 49 50 v vly2 ? 4/3 ? 5 (mv) v vly4 ? 2/5 ? 3 (mv) v vly4 ? 7/5 ? 8 (mv) v vly7 ? 4/8 ? 5 (mv) v vly7 ? 11/8 ? 12 (mv) v vly11 ? 7/12 ? 8 (mv) 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120
NCL30082 http://onsemi.com 13 typical characteristics figure 33. v vly11 ? 13/12 ? 15 vs. junction temperature figure 34. v vly13 ? 11/15 ? 12 vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 14.70 14.75 14.80 14.90 14.95 15.00 15.10 17.0 17.5 18.0 18.5 19.5 20.0 20.5 21.0 figure 35. v dim(en) vs. junction temperature figure 36. v dim(100) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 0.690 0.695 0.700 0.705 0.710 2.42 2.43 2.44 2.45 2.46 figure 37. t ovld vs. junction temperature figure 38. t recovery vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 84.0 84.5 85.0 85.5 86.0 87.0 87.5 88.0 4.30 4.35 4.40 4.45 4.50 4.55 v vly11 ? 13/12 ? 15 (mv) v vly13 ? 11/15 ? 12 (mv) v dim(en) (v) v dim(100) (v) t ovld (ms) t recovery (s) 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 14.85 15.05 19.0 86.5
NCL30082 http://onsemi.com 14 typical characteristics figure 39. v ovp vs. junction temperature figure 40. i otp(ref) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 2.470 2.475 2.480 2.485 2.490 2.495 2.500 83.0 83.5 84.0 84.5 85.0 85.5 86.0 86.5 figure 41. v otp(on) , v tf(stop) vs. junction temperature figure 42. v tf(start) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 0.680 0.682 0.684 0.686 0.688 0.690 0.985 0.987 0.989 0.991 0.993 0.995 0.997 figure 43. v bo(on) vs. junction temperature figure 44. v bo(off) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 0.982 0.984 0.986 0.988 0.990 0.992 0.994 0.896 0.898 0.900 0.902 0.904 0.906 v ovp (v) i otp(ref) ( a) v otp(on) , v tf(stop) (v) v tf(start) (v) v bo(on) (v) v bo(off) (v) 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120
NCL30082 http://onsemi.com 15 typical characteristics figure 45. t bo(blank) vs. junction temperature t j , junction temperature ( c) 52.5 53.0 53.5 54.0 54.5 55.0 55.5 56.0 t bo(blank) (ms) 100 80 60 40 20 0 ? 20 ? 40 120 application information the NCL30082 implements a current ? mode architecture operating in quasi ? resonant mode. thanks to proprietary circuitry, the controller is able to accurately regulate the secondary side current of the flyback converter without using any opto ? coupler or measuring directly the secondary side current. ? quasi ? resonance current ? mode operation: implementing quasi ? resonance operation in peak current ? mode control, the NCL30082 optimizes the efficiency by switching in the valley of the mosfet drain ? source voltage. thanks to a smart control algorithm, the controller locks ? out in a selected valley and remains locked until the input voltage or the output current set point significantly changes. ? primary side constant current control: thanks to a proprietary circuit, the controller is able to compensate for the leakage inductance of the transformer and allow accurate control of the secondary side current. ? line feed ? forward: compensation for possible variation of the output current caused by system slew rate variation. ? open led protection: if the voltage on the vcc pin exceeds an internal limit, the controller shuts down and waits 4 seconds before restarting switching. ? thermal fold ? back / over temperature / over voltage protection: by combining a dual threshold on the sd pin, the controller allows the direct connection of an ntc to ground plus a zener diode to a monitored voltage. the temperature is monitored and the output current is linearly reduced in the event that the temperature exceeds a prescribed level. if the temperature continues to increase, the current will be further reduced until the controller is stopped. the control will automatically restart if the temperature is reduced. this pin can implement a programmable ovp shutdown that can also auto ? restart the device. ? brown ? out: the controller includes a brown ? out circuit which safely stops the controller in case the input voltage is too low. the device will automatically restart if the line recovers. ? cycle ? by ? cycle peak curr ent limit: when the current sense voltage exceeds the internal threshold v ilim , the mosfet is turned off for the rest of the switching cycle. ? winding short ? circuit protection: an additional comparator with a short leb filter (t bcs ) senses the cs signal and stops the controller if v cs reaches 1.5 x v ilim . for noise immunity reasons, this comparator is enabled only during the main leb duration t leb . ? output short ? circuit protection: if a very low voltage is applied on zcd pin for 90 ms (nominal), the controllers assume that the output or the zcd pin is shorted to ground and enters shutdown. the auto ? restart version (b suffix) waits 4 seconds, then the controller restarts switching. in the latched version (a suffix), the controller is latched as long as v cc stays above the v cc(reset) threshold. ? linear or pwm dimming: the dim pin allows implementing both analog and pwm dimming.
NCL30082 http://onsemi.com 16 constant current control figure 47 portrays the primary and secondary current of a flyback converter in discontinuous conduction mode (dcm). figure 46 shows the basic circuit of a flyback converter. . . drv clamping network transformer figure 46. basic flyback converter schematic c lump r sense v out n sp l p l leak v bulk c clp r clp during the on ? time of the mosfet, the bulk voltage v bulk is applied to the magnetizing and leakage inductors l p and l leak and the current ramps up. when the mosfet is turned ? off, the inductor current first charges c lump . the output diode is off until the voltage across l p reverses and reaches: n sp v out v f (eq. 1) the output diode current increase is limited by the leakage inductor. as a consequence, the secondary peak current is reduced: i d,pk i l,pk n sp (eq. 2) the diode current reaches its peak when the leakage inductor is reset. thus, in order to accurately regulate the output current, we need to take into account the leakage inductor current. this is accomplished by sensing the clamping network current. practically, a node of the clamp capacitor is connected to r sense instead of the bulk voltage v bulk . then, by reading the voltage on the cs pin, we have an image of the primary current (red curve in figure 47). when the diode conducts, the secondary current decreases linearly from i d,pk to zero. when the diode current has turned off, the drain voltage begins to oscillate because of the resonating network formed by the inductors ( l p +l leak ) and the lump capacitor. this voltage is reflected on the auxiliary winding wired in flyback mode. thus, by looking at the auxiliary winding voltage, we can detect the end of the conduction time of secondary diode. the constant current control block picks up the leakage inductor current, the end of conduction of the output rectifier and controls the drain current to maintain the output current constant. we have: i out v ref 2n sp r sense (eq. 3) the output current value is set by choosing the sense resistor: r sense v ref 2n sp i out (eq. 4) from equation 3, the first key point is that the output current is independent of the inductor value. moreover, the leakage inductance does not influence the output current value as the reset time is taken into account by the controller.
NCL30082 http://onsemi.com 17 time time figure 47. flyback currents and auxiliary winding voltage in dcm v aux (t) t on t demag t 1 t 2 i sec (t) i pri (t) n sp i d,pk i l,pk internal soft ? start at startup or after recovering from a fault, there is a small internal soft ? start of 40 s. in addition, during startup, as the output voltage is zero volts, the demagnetization time is long and the constant current control block will slowly increase the peak current towards its nominal value as the output voltage grows. figure 48 shows a soft ? start simulation example for a 9 w led power supply.
NCL30082 http://onsemi.com 18 figure 48. startup simulation showing the natural soft ? start 0 4.00 8.00 12.0 16.0 1 0 200m 400m 600m 800m 2 604u 1.47m 2.34m 3.21m time in seconds 4.07m 0 200m 400m 600m 800m 3 4 i out v cs v out v control (a) (v) (v) cycle ? by ? cycle current limit when the current sense voltage exceeds the internal threshold v ilim , the mosfet is turned off for the rest of the switching cycle (figure 49). winding and output diode short ? circuit protection in parallel with the cycle ? by ? cycle sensing of the cs pin, another comparator with a reduced leb (t bcs ) and a higher threshold (1.5 v typical) is able to sense winding short ? circuit and immediately stops the drv pulses. the controller goes into auto ? recovery mode in version b. in version a, the controller is latched. in latch mode, the drv pulses stop and vcc ramps up and down. the circuit un ? latches when vcc pin voltage drops below v cc(reset) threshold.
NCL30082 http://onsemi.com 19 figure 49. winding short circuit protection, max. peak current limit circuits s r q cs rsense leb1 + ? s r q vcc aux vcc management vdd grand reset drv ipkmax pwmreset vccstop + ? leb2 wod_scp vcontrol + ? stop from fault management block ovp uvlo s r q grand reset ovp 8_hicc off wod_scp latch latch 8_hicc v ilimit v cs(stop) q q q thermal fold ? back and over voltage / over temperature protection the thermal fold ? back circuit reduces the current in the led string when the ambient temperature exceeds a set point. the current is gradually reduced to 50% of its nominal value if the temperature continues to rise. (figure 50). the thermal foldback starting temperature depends of the negative coef ficient t emperature (ntc) resistor chosen by the power supply designer. indeed, the sd pin allows the direct connection of an ntc to sense the ambient temperature. when the sd pin voltage v sd drops below v tf(start) , the internal reference for the constant current control v ref is decreased proportionally to v sd . when v sd reaches v tf(stop) , v ref is clamped to v ref50 , corresponding to 50% of the nominal output current. if v sd drops below v otp , the controller enters into the auto ? recovery fault mode for version b, meaning that the 4 ? s timer is activated. the controller will re ? start switching after the 4 ? s timer has elapsed and when v sd > v otp(on) to provide some temperature hysteresis (around 10 c). for version a, this protection is latched: reset occurs when v cc < v cc(reset) . the thermal fold ? back and otp thresholds correspond roughly to the following resistances: ? thermal fold ? back starts when r ntc 11.76 k . ? thermal fold ? back stops when r ntc 8.24 k . ? otp triggers when r ntc 5.88 k . ? otp is removed when r ntc 8.24 k . temperature increases temperature decreases shutdown figure 50. output current reduction versus sd pin voltage v sd v tf(start) v tf(stop) v otp(off) v otp(on) i out i out(nom) 50% i out(nom)
NCL30082 http://onsemi.com 20 at startup, when v cc reaches v cc(on) , the controller is not allowed to start pulsing for at least 180 s in order to allow the sd pin voltage to reach its nominal value if a filtering capacitor is connected to the sd pin. this is to avoid flickering of the led light in case of over temperature. s r q vccreset sd vcc + ? vdd + ? otp_timer end noise delay noise delay clamp rclamp vclamp latch ntc dz otp ovp (otp latched for version a) s r q 4 ? s timer off 0.5 v if otp low 0.7 v if otp high figure 51. thermal fold ? back and ovp/otp circuitry v ovp i otp(ref) v tf v otp q q in the case of excess voltage, the zener diode starts to conduct and inject current into the internal clamp resistor r clamp thus causing the pin sd voltage to increase. when this voltage reaches the ovp threshold (2.5 v typ.), the controller shuts ? down and waits for at least 4 seconds before restarting switching.
NCL30082 http://onsemi.com 21 4 ? s timer figure 52. ovp with sd pin chronograms v cc > v cc(on) : drv pulses restart 4 ? s timer has elapsed: waiting for v cc > v cc(on) to restart drv pulses v out v sd(clamp) v ovp v sd v drv v sd > v ovp : controller stops switching v cc v cc(on) v cc(off) v cc(reset)
NCL30082 http://onsemi.com 22 4 ? s timer figure 53. thermal fold ? back / otp chronograms i out v otp(off) v tf(stop) v sd v drv v cc v cc(on) v cc(off) v cc(reset) v tf(start) v sd > v tf(stop) and v cc > v cc(on) : drv pulses restart 4 ? s timer has elapsed but v sd < v tf(stop) no restart v sd < v otp(off) : controller stops switching pwm or linear dimming detection the pin dim allows implementing either linear dimming or pwm dimming of the led light. if the power supply designer apply an analog signal varying from v dim(en) to v dim100 to the dim pin, the output current will increase or decrease proportionally to the voltage applied. for v dim = v dim100 , the power supply delivers the maximum output current. if a voltage lower than v dim(en) is applied to the dim pin, the drv pulses are disabled. thus, for pwm dimming, a pwm signal with a low state value < v dim(en) and a high state value > v dim100 should be applied. the dim pin is pulled up internally by a small current source. thus, if the pin is left open, the controller is able to start. 0% 100% pwm dimming analog dimming figure 54. pin dim chronograms v dim i out i out v dim(en) v dim100 note : ? if a pwm voltage with a high state value < v dim100 is applied to the dim pin, the product will still be in pwm dimming mode, but the reference voltage will be decreased according to v dim . this allows increased dynamic range on the dimming control pin. ? thermal foldback and dimming: if the ic is in a dimming state and the thermal foldback (tf) is activated, the output current is further reduced to a value equal to dimming*tf.
NCL30082 http://onsemi.com 23 v cc over voltage protection (open led protection) if no output load is connected to the led power supply, the controller must be able to safely limit the output voltage excursion. in the NCL30082, when the v cc voltage reaches the v cc(ovp) threshold, the controller stops the drv pulses and the 4 ? s timer starts counting. the ic re ? start pulsing after the 4 ? s timer has elapsed and when v cc v cc(on) . figure 55. open led protection chronograms 0 10.0 20.0 30.0 40.0 1 0 10.0 20.0 30.0 40.0 2 0 200m 400m 600m 800m 3 1.38 3.96 6.54 9.11 11.7 time in seconds 0 2.00 4.00 6.00 8.00 4 v cc(on) v cc(ovp) v cc(off) v out i out v cc ovp (v) (a) (v) (v) valley lockout quasi ? square wave resonant systems have a wide switching frequency excursion. the switching frequency increases when the output load decreases or when the input voltage increases. the switching frequency of such systems must be limited. the NCL30082 changes the valley as the input voltage increases and as the output current set ? point is varied (dimming and th ermal fold ? back). this limits the switching frequency excursion. once a valley is selected, the controller stays locked in the valley until the input voltage or the output current set ? point varies significantly. this avoids valley jumping and the inherent noise caused by this phenomenon. the input voltage is sensed by the vin pin (line range detection in figure 56). the internal logic selects the operating valley according to vin pin voltage, sd pin voltage and dim pin voltage. by default, when the output current is not dimmed, the controller operates in the first valley at low line and in the second valley at high line.
NCL30082 http://onsemi.com 24 + ? vbulk vin lline 25 ? ms blanking time hline 2.4 v if lline low 2.3 v if lline high figure 56. line range detector table 4. valley selection i out value at which the controller changes valley (i out decreasing) vin pin voltage for valley change i out value at which the controller changes valley (i out increasing) v vin decreases 0 ? ll ? 2.3 v ? hl ? 5 v i out decreases 100% 1 st 2 nd 100% i out increases 75% 78% 2 nd 3 rd 50% 53% 4 th 5 th 30% 33% 7 th 8 th 15% 20% 11 th 12 th 6% 8% 13 th 15 th 0% 0% 0 ? ll ? 2.4 v ? hl ? 5 v v vin increases vin pin voltage for valley change
NCL30082 http://onsemi.com 25 zero crossing detection block the zcd pin allows detecting when the drain ? source voltage of the power mosfet reaches a valley. a valley is detected when the voltage on pin 1 crosses below the v zcd(thd) internal threshold. at startup or in case of extremely damped free oscillations, the zcd comparator may not be able to detect the valleys. to avoid such a situation, the NCL30082 features a time ? out circuit that generates pulses if the voltage on zcd pin stays below the v zcd(thd) threshold for 6.5 s. the time ? out also acts as a substitute clock for the valley detection and simulates a missing valley in case of too damped free oscillations. figure 57. time ? out chronograms 4 3 14 12 15 16 17 low high clk timeout low high low high low high zcd comp 2nd, v zcd the 3rd valley is not detected by the zcd comp time ? out circuit adds a pulse to account for the missing 3rd valley the 2nd valley is detected by the zcd comparator v zcd(thd) the 3rd valley is validated 3rd normally with this type of time ? out function, in the event the zcd pin or the auxiliary winding is shorted, the controller could continue switching leading to improper regulation of the led current. moreover during an output short circuit, the controller will strive to maintain constant current operation. to avoid these scenarios, a protection circuit consisting of a comparator and secondary timer starts counting when the zcd voltage is below the v zcd(short) threshold. if this timer reaches 90 ms, the controller detects a fault and shutdown. the auto ? restart version (b suffix) waits 4 seconds, then the controller restarts switching. in the latched version (a suffix), the controller is latched as long as v cc stays above the v cc(reset) threshold.
NCL30082 http://onsemi.com 26 + ? zcd time ? out tblank clock + ? tblank s r q aux_scp 4 ? s timer enable_b 90 ? ms timer . figure 58. zcd block schematic v zcd(th) v zcd(short) q line feed ? forward because of the propagation delays, the mosfet is not turned ? off immediately when the current set ? point is reached. as a result, the primary peak current is higher than expected and the output current increases. to compensate the peak current increase brought by the propagation delay, a positive voltage proportional to the line voltage is added on the current sense signal. the amount of of fset voltage can be adjusted using the r cs resistor as shown in figure 59. v cs(offset) k lff v pinvin r cs (eq. 5) the offset voltage is applied only during the mosfet on ? time. this offset voltage is removed at light load during dimming when the output current drops below 15% of the programmed output current. bulk rail vin cs q_drv offset_ok figure 59. line feed ? forward schematic v dd i cs(offset) r cs r sense
NCL30082 http://onsemi.com 27 brown ? out in order to protect the supply against a very low input voltage, the NCL30082 features a brown ? out circuit with a fixed on/off threshold. the controller is allowed to start if a voltage higher than 1 v is applied to the vin pin and shuts ? down if the vin pin voltage decreases and stays below 0.9 v for 50 ms nominal. exiting a brown ? out condition overrides the hiccup on v cc (v cc does not wait to reach v cc(off) ) and the ic immediately goes into startup mode (i cc = i cc(start) ). + ? vbulk vin bo_nok 50 ? ms blanking time 1 v if bonok high 0.9 v if bonok low figure 60. brown ? out circuit figure 61. brown ? out chronograms (valley fill circuit is used) 0 40.0 80.0 120 160 1 10.0 12.0 14.0 16.0 18.0 2 300m 500m 700m 900m 1.10 3 46.1m 138m 231m 323m 415m time in seconds 0 2.00 4.00 6.00 8.00 4 v cc v bulk v pinvin bo_nok (v) (v) (v) (v) bo_nok low => startup mode 50 ? ms timer v bo(on) v bo(off) v cc(on) v cc(off)
NCL30082 http://onsemi.com 28 cs pin short circuit protection normally, if the cs pin or the sense resistor is shorted to ground, the driver will not be able to turn off, leading to potential damage of the power supply. to avoid this, the NCL30082 features a circuit to protect the power supply against a short circuit of the cs pin. when the mosfet is on, if the cs voltage stays below v cs(low) after the adaptive blanking timer has elapsed, the controller shuts down and will attempt to restart on the next v cc hiccup. + ? cs q_drv cs_short s r q uvlo bo_nok adaptative blanking time figure 62. cs pin short circuit protection schematic q v cs(low) v vin fault management off mode the circuit turns off whenever a major condition prevents it from operating: ? incorrect feeding of the circuit: ?uvlo high?. the uvlo signal becomes high when v cc drops below v cc(off) and remains high until v cc exceeds v cc(on) . ? otp ? v cc ovp ? ovp2 (additional ovp provided by sd pin) ? output diode short circuit protection: ?wod_scp high? ? output / auxiliary winding short circuit protection: ?aux_scp high? ? die over temperature (tsd) ? brown ? out: ?bo_nok? high ? pin cs short circuited to gnd: ?cs_short high? in this mode, the drv pulses are stopped. the vcc voltage decrease through the controller own consumption (i cc1 ). for the output diode short circuit protection, the cs pin short circuit protection, the output / aux. winding short circuit protection and the ovp2, the controller waits 4 seconds (auto ? recovery timer) and then initiates a startup sequence (v cc v cc(on) ) before re ? starting switching. latch mode this mode is activated by the output diode short ? circuit protection (wod_scp), the otp and the aux ? scp in version a only. in this mode, the drv pulses are stopped and the controller is latched. there are hiccups on v cc . the circuit un ? latches when v cc < v cc(reset) .
NCL30082 http://onsemi.com 29 reset stop 4 ? s timer run bo_nok high or otp or tsd or cs_short ovp2 or wod_scp or aux_scp timer has finished counting bo_nok high or otp or tsd or cs_short figure 63. state diagram for b version faults or v cc _ovp v cc > v cc(on) v cc < v cc(off) v cc disch. v cc < v cc(off) or bo_nok ovp2 or v cc _ovp with states : reset stop run v cc disch. 4 ? s timer controller is reset, i cc = i cc(start) controller is on, drv is not switching, t otp(start) has elapsed normal switching no switching, i cc = i cc1 , waiting for v cc to decrease to v cc(off) the auto ? recovery timer is counting, v cc is ramping up and down between v cc(on) and v cc(off)
NCL30082 http://onsemi.com 30 figure 64. state diagram for a version faults with states : reset stop run v cc disch. 4 ? s timer latch controller is reset, i cc = i cc(start) controller is on, drv is not switching, t otp(start) has elapsed normal switching no switching, i cc = i cc1 , waiting for v cc to decrease to v cc(off) the auto ? recovery timer is counting, v cc is ramping up and down between v cc(on) and v cc(off) controller is latched off, v cc is ramping up and down between v cc(on) and v cc(off) , only v cc(reset) can release the latch. reset stop 4 ? s timer run bo_nok high or tsd or cs_short latch wod_scp or aux_scp timer has finished counting bo_nok high or tsd or cs_short v cc > v cc(on) v cc < v cc(off) v cc disch. v cc < v cc(off) or bo_nok ovp2 or v cc _ovp otp or v cc < v cc(reset) ovp2 or v cc _ovp otp
NCL30082 http://onsemi.com 31 package dimensions micro8 case 846a ? 02 issue h s b m 0.08 (0.003) a s t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. 846a-01 obsolete, new standard 846a-02. b e pin 1 id 8 pl 0.038 (0.0015) ? t ? seating plane a a1 c l *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 8x 8x 6x mm inches scale 8:1 1.04 0.041 0.38 0.015 5.28 0.208 4.24 0.167 3.20 0.126 0.65 0.0256 dim a min nom max min millimeters ?? ?? 1.10 ?? inches a1 0.05 0.08 0.15 0.002 b 0.25 0.33 0.40 0.010 c 0.13 0.18 0.23 0.005 d 2.90 3.00 3.10 0.114 e 2.90 3.00 3.10 0.114 e 0.65 bsc l 0.40 0.55 0.70 0.016 ?? 0.043 0.003 0.006 0.013 0.016 0.007 0.009 0.118 0.122 0.118 0.122 0.026 bsc 0.021 0.028 nom max 4.75 4.90 5.05 0.187 0.193 0.199 h e h e d d e
NCL30082 http://onsemi.com 32 options controller output scp winding/output diode scp over temperature protection NCL30082a latched latched latched NCL30082b auto ? recovery auto ? recovery auto ? recovery ordering information device package marking package type shipping ? NCL30082admr2g aac micro8 (pb ? free,halide ? free) 4000 / tape & reel NCL30082bdmr2g aad micro8 (pb ? free,halide ? free) 4000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCL30082/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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